1. Technical Field
The present invention relates to technology for regulating the oscillation frequency of an oscillation circuit, and for example to an oscillation frequency regulating circuit, a semiconductor device, an electronic device, and an oscillation frequency regulation method suitable for performing high precision regulation quickly.
2. Related Art
A trimming circuit is provided in an oscillation circuit for automatic regulation of the oscillation frequency of an oscillator. For example an automatic trimming circuit for an oscillator is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2001-285056. The trimming circuit is equipped with: a variable frequency CR oscillation circuit of comparatively low oscillation frequency precision; a quartz oscillation circuit of comparatively high oscillation frequency precision; a control logic circuit that generates a latch signal at a specific timing based on the oscillation frequency of the quartz oscillation circuit; a counter that counts an output clock signal of the CR oscillation circuit; and a data comparator circuit that compares counter output data of the counter latched to the latch signal against specific reference data, outputs a binary m-bit trimming signal that varies according to the difference between both inputs so as to control to change the oscillation frequency of the CR oscillation circuit, and stops control operation when the difference between both inputs is within a determined range.
Explanation follows regarding configuration and operation of a related oscillation frequency regulating circuit that regulates the oscillation frequency of an oscillator using a trimming signal, with reference to FIG. 7 and FIG. 8.
As illustrated in FIG. 7, an oscillation frequency regulating circuit for regulating the oscillation operation of a CR oscillation circuit 2 is configured including a trimming circuit 1, a NBit counter (referred to below simply as counter) 3, a comparator 4, D flip-flop circuits (referred to below simply as flip-flops) DFF0 to DFF3, a NOR circuit (logical NOT-OR operation circuit) SUB 3, a OR circuits (logical OR circuits) SUB 0 to SUB 2, a NOT circuit (NOT circuit) SUB 4, and an AND circuit (logical AND circuit) SUB 5.
Due to the above configuration, the related oscillation frequency regulating circuit operates the counter 3 for a fixed duration count according to the clock of the CR oscillation circuit 2, performs overflow determination in the comparator 4 based on a comparison of count result data of the counter 3 against a predetermined overflow value, and determines a trimming value for employing to regulate the oscillation frequency of the CR oscillation circuit 2 based on results of overflow determination.
In FIG. 7, for example 4-bit trimming setting values of li_trm3, li_trm2, li_trm1 and li_trm0 input from an external device such as a tester connected during oscillation frequency regulation are respectively input as clocks to the flip-flops DFF3 to DFF0, and also input as one of the inputs of the NOR circuit SUB 3, the OR circuit SUB 2, the OR circuit SUB 1, and the OR circuit SUB 0.
Note that in this example the highest order bit trimming setting value is li_trm3, and the lowest order bit trimming setting value is li_trm0.
The respective outputs of the flip-flops DFF3 to DFF0 are input to the other inputs of the NOR circuit SUB 3 and the OR circuits SUB 2 to SUB 0.
The respective outputs of the NOR circuit SUB 3 and the OR circuits SUB 2 to SUB 0 are input as data inputs to the trimming circuit 1.
A counter operation duration setting signal employed to control the counter operation duration of the counter 3 is shown as co_en. The counter operation duration setting signal co_en is input as one of the inputs to the AND circuit SUB 5, and the output of the CR oscillation circuit 2 is input as the other input to the AND circuit SUB 5.
The output of the AND circuit SUB 5 is input as the clock input to the counter 3, and a co_rst signal is input from an external device to the counter 3 as a reset signal.
The output of the counter 3 is input as one input to the comparator 4, and the output of the comparator 4 is input to the NOT circuit SUB 4. The output of the NOT circuit SUB 4 is input as data input respectively to the flip-flops DFF3 to DFF0.
Explanation follows regarding automatic trimming operation of the oscillation frequency regulating circuit configured as described above, with reference to a timing chart that is illustrated in FIG. 8.
Note that the relationship between the trimming value and the oscillation frequency is, as schematically illustrated in FIG. 9, such that the oscillation frequency becomes the highest (fastest) when the value input to the trimming circuit 1 corresponding to the highest order bit trimming setting value li_trm3 is “0” and the values input to the trimming circuit 1 corresponding to each of the following bit trimming setting values li_trm2 to li_trm0 are “1” (“0111”), such that the oscillation frequency becomes the lowest (slowest) when the value input to the trimming circuit 1 corresponding to the highest order bit trimming setting value li_trm3 is “1” and the values input to the trimming circuit 1 corresponding to each of the following bit trimming setting values li_trm2 to li_trm0 are “0” (“1000”), and such that the oscillation frequency is an intermediate frequency when the trimming setting values li_trm3 to li_trm0 are all “0”.
In FIG. 7, when first the trimming setting value li_trm3 is input as “H”, namely “1”, and the trimming setting values li_trm2 to li_trm0 are input as “L”, namely “0”, the trimming circuit 1 is input with “0000” as the trimming value by the flip-flops DFF3 to DFF0, the NOR circuit SUB 3 and the OR circuits SUB 2 to SUB 0.
For example, this state is an initial state after each of the flip-flops DFF3 to DFF0 have been reset, and when the trimming setting value li_trm3 is made “H (1)” without operating each of the flip-flops DFF3 to DFF0, then only the trimming setting value li_trm3 “H (1)” and the trimming setting values li_trm2 to li_trm0 “L (0)” are input to the NOR circuit SUB 3 and the OR circuits SUB 2 to SUB 0, the trimming setting value li_trm3 “H (1)” is inverted in the NOR circuit SUB 3 to “L (0)”, and as a result the trimming value “0000” is input to the trimming circuit 1.
Based on this input trimming value, the trimming circuit 1 generates a control signal employed to regulate circuit elements such as resistors and capacitors in the CR oscillation circuit 2 used to set the oscillation frequency, and outputs the control signal to the CR oscillation circuit 2. The CR oscillation circuit 2 accordingly oscillates at the intermediate frequency corresponding to the trimming value “0000”.
In this state, an external device operates the counter 3 for a predetermined duration (referred to below simply as a specific duration) by making the counter operation duration setting signal co_en “H (1)”, and the counter 3 counts (measures) the oscillation frequency of the CR oscillation circuit 2.
The counter values of the counter 3 are serially input to the comparator 4 and the comparator 4 compares the counter values of the counter 3 against an overflow value. When the “counter value>overflow value” occurs within the specific duration, the comparator 4 outputs “H (1)” as an overflow signal ov. Note that the output of the comparator 4 remains at “L (0)” when “counter value>overflow value” does not occur within the specific duration.
The counter operation duration setting signal co_en is made “L (0)” when the specific duration has elapsed, thereby stopping the counter operation of the counter 3.
In FIG. 8, when the trimming value “0000” is input, the counter value of the counter 3 does not reach the overflow value within the specific duration, and the overflow signal ov output from the comparator 4 is “L (0)”.
This output is inverted in the NOT circuit SUB 4 to “H (1)”, and input to the respective data input terminals of the flip-flops DFF3 to DFF0.
In this state, the trimming setting value from the external device is shifted from the higher order values in the counter operation duration of the counter 3 for the specific duration at the next time of regulation. Specifically, the trimming setting value li_trm3 is changed to “L (0)” and the trimming setting value li_trm2 is changed to “H (1)”.
When the trimming setting value li_trm3 and the trimming setting value li_trm2 are changed in this manner, the flip-flop DFF3 and the flip-flop DFF2 are latched to output “H (1)” from the NOT circuit SUB 4 being input to their data input terminals, and “H (1)” is output to the NOR circuit SUB 3 and the OR circuit SUB 2.
The output of the NOR circuit SUB 3 is thereby made “L (0)” and the output of the OR circuit SUB 2 is thereby made “H (1)”, and “0100” is input as the trimming value to the trimming circuit 1. As a result the CR oscillation circuit 2 oscillates at an oscillation frequency intermediate between the trimming value “0000” and the trimming value “0111”.
Namely, with oscillation at the intermediate oscillation frequency corresponding to the trimming value “0000”, since the counter value of the counter 3 does not reach the overflow value, the CR oscillation circuit 2 is caused to oscillate faster than oscillation at the intermediate frequency corresponding to trimming value “0000”, and at an intermediate frequency between those corresponding to the trimming value “0000” and the trimming value “0111”.
At this trimming value setting, as illustrated in FIG. 8, an “H (1)” overflow signal ov is output from the comparator 4 when the counter value of the counter 3 reaches the overflow value within the specific duration.
The overflow signal ov (H) from the comparator 4 is inverted by the NOT circuit SUB 4 to “L (0)”, and input to the respective data input terminals of each of the flip-flops DFF3 to DFF0.
Similarly, when in this state, the trimming setting value is shifted in the counter operation duration of the counter 3 of the specific duration at the next time of regulation, and the trimming setting value li_trm2 is changed to “L (0)” and the trimming setting value li_trm1 is changed to “H (1)”.
When the trimming setting value li_trm2 and the trimming setting value li_trm1 are changed in this manner, the flip-flop DFF2 and the flip-flop DFF1 are latched to the output “L (0)” from the NOT circuit SUB 4 that is being input to their data input terminals, and “L (0)” is output to the OR circuit SUB 2 and the OR circuit SUB 1.
The output of the OR circuit SUB 2 thereby is made “L (0)”, and the output of the OR circuit SUB 1 that is being input to one input terminal with the trimming setting value li_trm1 of “H (1)” is made “H (1)”, and the trimming circuit 1 is input with “0010” as the trimming value.
As a result the CR oscillation circuit 2 then oscillates this time at an intermediate frequency to those corresponding to the trimming value “0000” and the trimming value “0100”.
Namely, when oscillating at the frequency corresponding to the trimming value “0100”, since the counter value of the counter 3 reaches the overflow value within the specific duration, the CR oscillation circuit 2 is caused to oscillate slower than oscillation at the frequency corresponding to the trimming value “0100” and at a frequency intermediate between those corresponding to the trimming value “0000” and the trimming value “0100”.
When set at this trimming value (“0010”), as illustrated in FIG. 8, the counter value of the counter 3 also reaches the overflow value within the specific duration, and the overflow signal ov (H) of “H (1)” is output from the comparator 4.
The overflow signal ov (H) from the comparator 4 is inverted in the NOT circuit SUB 4 to “L (0)”, and “L (0)” is input to the respective data input terminals of each of the flip-flops DFF3 to DFF0.
Then, in this state, the trimming setting value is shifted for the counter operation duration of the counter 3 of the specific duration at the next time of regulation, with the trimming setting value li_trm1 changed to “L (0)” and the trimming setting value li_trm0 changed to “H (1)”.
When the trimming setting value li_trm1 and the trimming setting value li_trm0 are changed in this manner, the flip-flop DFF1 and the flip-flop DFF0 are latched to the output “L (0)” from the NOT circuit SUB 4 that is being input to their data input terminals, and “L (0)” is output to the OR circuit SUB 1 and the OR circuit SUB 0.
The output of the OR circuit SUB 2 is accordingly made “L (0)”, and the output of the OR circuit SUB 0 that is being input to one input with the trimming setting value li_trm0 of “H (1)” is made “H (1)”, and the trimming circuit 1 is input with “0001” as the trimming value.
As a result, the CR oscillation circuit 2 oscillates at a frequency intermediate between those corresponding to trimming value “0000” and the trimming value “0010”, namely a frequency corresponding to the trimming value “0001”.
Thus operation based on the trimming setting values li_trm3 to li_trm0 from the external device regulates the oscillation frequency of the CR oscillation circuit 2 to the optimum value by repeating the trimming bits worth of times, 4-bits worth of times in the examples of FIG. 7 to FIG. 9.
Note that whereas regulation is ended in a state in which the CR oscillation circuit 2 is oscillating at the frequency due to trimming value “0001” and the overflow signal ov is not being output from the comparator 4 in the example of FIG. 8, regulation may be ended in a state in which the overflow signal ov is being output from the comparator 4.
The related oscillation frequency regulating circuit thus determines the trimming value by operating a constant time counter using an oscillation source clock and performing overflow determination.
However, in the related oscillation frequency regulating circuit, the overflow value is a fixed value, and therefore the count duration also needs to be fixed, with an issue arising that this means that regulation and testing takes time.
Namely, when oscillation frequency regulation operation is executed, since the overflow value of the counter is fixed, there is a need to operate the counter for the predetermined fixed duration. There is also a need to operate the counter for the trimming bits worth of times, with an issue arising of an increase in the trimming duration. For example, when executing a counter at 8-bit precision for 100μ seconds oscillation frequency regulation operation, the regulation and test time is “100μ seconds×8=800μ seconds”, with the regulation and test duration increasing as the precision of trimming is raised.